logical operators

TODO.md

@@ -0,0 +1,2 @@
+# TODO List
+- arguments validation for each instruction

examples/loop.tasm

@@ -0,0 +1,12 @@
+/*
+Example of graphical application
+*/
+
+.main:
+
+le
+gt
+eq
+jif
+jel
+exit

examples/window.tasm

@@ -0,0 +1,9 @@
+/*
+Example of graphical application
+*/
+
+.main:
+
+jif
+jel
+exit

src/VM/time.c

@@ -10,9 +10,9 @@ void time_sleepNS(u64 ns){
 }
 
 u64 time_getMonotonicMS(){
-    SDL_GetTicks();
+    return SDL_GetTicks();
 }
 
 u64 time_getMonotonicNS(){
-    SDL_GetTicksNS();
+    return SDL_GetTicksNS();
 }

src/instructions/impl/logical_operators.c

@@ -0,0 +1,93 @@
+#include "impl_macros.h"
+
+#define logicalOperator1Impl(NAME, OPERATOR)\
+i32 NAME##_impl (VM* vm) {\
+    u8 src_register_i = 0;\
+    readRegisterVar(src_register_i);\
+    /*u8 value_size = 0;\
+    readValueSizeVar(value_size);*/\
+    u8 value_size = 4;\
+    \
+    switch(value_size){\
+        case 1: \
+            vm->registers.array[src_register_i].u8v0 = OPERATOR vm->registers.array[src_register_i].u8v0;\
+            break;\
+        case 2: \
+            vm->registers.array[src_register_i].u16v0 = OPERATOR vm->registers.array[src_register_i].u16v0;\
+            break;\
+        case 4: \
+            vm->registers.array[src_register_i].u32v0 = OPERATOR vm->registers.array[src_register_i].u32v0;\
+            break;\
+        case 8: \
+            vm->registers.array[src_register_i].u64v = OPERATOR vm->registers.array[src_register_i].u64v;\
+            break;\
+    }\
+    return sizeof(src_register_i) + sizeof(value_size);\
+}
+
+#define logicalOperator2Impl(NAME, OPERATOR)\
+i32 NAME##_impl (VM* vm) {\
+    u8 dst_register_i = 0, src_register_i = 0;\
+    readRegisterVar(dst_register_i);\
+    readRegisterVar(src_register_i);\
+    /*u8 value_size = 0;\
+    readValueSizeVar(value_size);*/\
+    u8 value_size = 4;\
+    \
+    switch(value_size){\
+        case 1: \
+            vm->registers.array[dst_register_i].u8v0 OPERATOR##= vm->registers.array[src_register_i].u8v0;\
+            break;\
+        case 2: \
+            vm->registers.array[dst_register_i].u16v0 OPERATOR##= vm->registers.array[src_register_i].u16v0;\
+            break;\
+        case 4: \
+            vm->registers.array[dst_register_i].u32v0 OPERATOR##= vm->registers.array[src_register_i].u32v0;\
+            break;\
+        case 8: \
+            vm->registers.array[dst_register_i].u64v OPERATOR##= vm->registers.array[src_register_i].u64v;\
+            break;\
+    }\
+    return sizeof(dst_register_i) + sizeof(src_register_i) + sizeof(value_size);\
+}
+
+#define logicalOperator3Impl(NAME, OPERATOR)\
+i32 NAME##_impl (VM* vm) {\
+    u8 dst_register_i = 0, src0_register_i = 0, src1_register_i = 0;\
+    readRegisterVar(dst_register_i);\
+    readRegisterVar(src0_register_i);\
+    readRegisterVar(src1_register_i);\
+    /*u8 value_size = 0;\
+    readValueSizeVar(value_size);*/\
+    u8 value_size = 4;\
+    \
+    switch(value_size){\
+        case 1: \
+            vm->registers.array[dst_register_i].u8v0 = vm->registers.array[src0_register_i].u8v0 OPERATOR vm->registers.array[src1_register_i].u8v0;\
+            break;\
+        case 2: \
+            vm->registers.array[dst_register_i].u16v0 = vm->registers.array[src0_register_i].u16v0 OPERATOR vm->registers.array[src1_register_i].u16v0;\
+            break;\
+        case 4: \
+            vm->registers.array[dst_register_i].u32v0 = vm->registers.array[src0_register_i].u32v0 OPERATOR vm->registers.array[src1_register_i].u32v0;\
+            break;\
+        case 8: \
+            vm->registers.array[dst_register_i].u64v = vm->registers.array[src0_register_i].u64v OPERATOR vm->registers.array[src1_register_i].u64v;\
+            break;\
+    }\
+    return sizeof(dst_register_i) + sizeof(src0_register_i) + sizeof(src1_register_i) + sizeof(value_size);\
+}
+
+logicalOperator3Impl(EQ, ==)
+logicalOperator3Impl(NE, !=)
+logicalOperator3Impl(LT, <)
+logicalOperator3Impl(LE, <=)
+logicalOperator3Impl(GT, >)
+logicalOperator3Impl(GE, >=)
+
+logicalOperator1Impl(NOT, !)
+logicalOperator1Impl(INV, ~)
+
+logicalOperator2Impl(OR, |)
+logicalOperator2Impl(XOR, ^)
+logicalOperator2Impl(AND, &)

src/instructions/impl/math_operators.c

@@ -1,6 +1,7 @@
 #include "impl_macros.h"
 
-#define mathOperatorImpl(OPERATOR){\
+#define mathOperator2Impl(NAME, OPERATOR)\
+i32 NAME##_impl (VM* vm) {\
     u8 dst_register_i = 0, src_register_i = 0;\
     readRegisterVar(dst_register_i);\
     readRegisterVar(src_register_i);\
@@ -26,26 +27,16 @@
 }
 
 /// ADD [dst_register] [src_register]
-i32 ADD_impl(VM* vm){
+mathOperator2Impl(ADD, +)
-    mathOperatorImpl(+);
-}
 
 /// SUB [dst_register] [src_register]
-i32 SUB_impl(VM* vm){
+mathOperator2Impl(SUB, -)
-    mathOperatorImpl(-);
-}
 
 /// MUL [dst_register] [src_register]
-i32 MUL_impl(VM* vm){
+mathOperator2Impl(MUL, *)
-    mathOperatorImpl(*)
-}
 
 /// DIV [dst_register] [src_register]
-i32 DIV_impl(VM* vm){
+mathOperator2Impl(DIV, /)
-    mathOperatorImpl(/)
-}
 
 /// MOD [dst_register] [src_register]
-i32 MOD_impl(VM* vm){
+mathOperator2Impl(MOD, %)
-    mathOperatorImpl(%)
-}

src/instructions/instructions.c

@@ -2,32 +2,65 @@
 #include "../collections/HashMap.h"
 
 i32 NOP_impl(VM* vm);
+i32 EXIT_impl(VM* vm);
+i32 SYS_impl(VM* vm);
+
 i32 MOVC_impl(VM* vm);
 i32 MOVR_impl(VM* vm);
+
 i32 ADD_impl(VM* vm);
 i32 SUB_impl(VM* vm);
 i32 MUL_impl(VM* vm);
 i32 DIV_impl(VM* vm);
 i32 MOD_impl(VM* vm);
-i32 SYS_impl(VM* vm);
+
-i32 EXIT_impl(VM* vm);
+i32 EQ_impl(VM* vm);
+i32 NE_impl(VM* vm);
+i32 LT_impl(VM* vm);
+i32 LE_impl(VM* vm);
+i32 GT_impl(VM* vm);
+i32 GE_impl(VM* vm);
+i32 NOT_impl(VM* vm);
+i32 INV_impl(VM* vm);
+i32 OR_impl(VM* vm);
+i32 XOR_impl(VM* vm);
+i32 AND_impl(VM* vm);
+
 i32 JMP_impl(VM* vm);
-i32 CALL_impl(VM* vm);
+i32 JIF_impl(VM* vm);
+i32 JEL_impl(VM* vm);
+
 
 Array_declare(Instruction);
 static const Array_Instruction instructions_array = ARRAY(Instruction, {
     Instruction_construct(NOP),
+    Instruction_construct(EXIT),
+    Instruction_construct(SYS),
+
     Instruction_construct(MOVC),
     Instruction_construct(MOVR),
+    
     Instruction_construct(ADD),
     Instruction_construct(SUB),
     Instruction_construct(MUL),
     Instruction_construct(DIV),
     Instruction_construct(MOD),
-    Instruction_construct(SYS),
+
-    Instruction_construct(EXIT),
+    Instruction_construct(EQ),
-    // Instruction_construct(JMP),
+    Instruction_construct(NE),
-    // Instruction_construct(CALL),
+    Instruction_construct(LT),
+    Instruction_construct(LE),
+    Instruction_construct(GT),
+    Instruction_construct(GE),
+    Instruction_construct(NOT),
+    Instruction_construct(INV),
+    Instruction_construct(OR),
+    Instruction_construct(XOR),
+    Instruction_construct(AND),
+    
+    Instruction_construct(JMP),
+    Instruction_construct(JIF),
+    Instruction_construct(JEL),
 });
 
 const Instruction* Instruction_getByOpcode(Opcode opcode){

src/instructions/instructions.h

@@ -7,15 +7,33 @@ typedef i32 (*InstructionImplFunc_t)(VM* vm);
 
 typedef enum __attribute__((__packed__)) Opcode {
     Opcode_NOP,
+    Opcode_EXIT,
+    Opcode_SYS,
+
     Opcode_MOVC,
     Opcode_MOVR,
+
     Opcode_ADD,
     Opcode_SUB,
     Opcode_MUL,
     Opcode_DIV,
     Opcode_MOD,
-    Opcode_SYS,
+
-    Opcode_EXIT,
+    Opcode_EQ,
+    Opcode_NE,
+    Opcode_LT,
+    Opcode_LE,
+    Opcode_GT,
+    Opcode_GE,
+    Opcode_NOT,
+    Opcode_INV,
+    Opcode_OR,
+    Opcode_XOR,
+    Opcode_AND,
+    
+    Opcode_JMP,
+    Opcode_JIF,
+    Opcode_JEL,
 } Opcode;
 
 typedef struct Instruction {