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refactored registers

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This commit is contained in:
Timerix
2025-04-18 02:46:46 +05:00
parent dd8c65ef79
commit ba72dae68f
18 changed files with 359 additions and 282 deletions
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36
src/instructions/impl/JMP.c
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@@ -2,7 +2,7 @@
// JUMP [destination address]
i32 JMP_impl(VM* vm){
u32 dst_addr = 0;
u64 dst_addr = 0;
readVar(dst_addr);
vm->current_pos = dst_addr;
@@ -13,28 +13,38 @@ i32 JMP_impl(VM* vm){
// JNZ [destination address] [condition register]
i32 JNZ_impl(VM* vm){
u32 dst_addr = 0;
u64 dst_addr = 0;
readVar(dst_addr);
u8 cond_register_i = 0;
readRegisterVar(cond_register_i);
if(vm->registers.array[cond_register_i].u32v0 != 0){
RegisterCode reg_code = 0;
readRegisterCode(reg_code);
u64 cond_reg_value = 0;
VM_registerRead(vm, &cond_reg_value, reg_code);
if(cond_reg_value != 0){
vm->current_pos = dst_addr;
}
return sizeof(dst_addr) + sizeof(cond_register_i);
return sizeof(dst_addr) + sizeof(reg_code);
}
// JZ [destination address] [condition register]
i32 JZ_impl(VM* vm){
u32 dst_addr = 0;
readVar(dst_addr);
u8 cond_register_i = 0;
readRegisterVar(cond_register_i);
if(vm->registers.array[cond_register_i].u32v0 == 0){
u64 dst_addr = 0;
{
if(!VM_dataRead(vm, &dst_addr, vm->current_pos, sizeof(dst_addr)))
return -1;
vm->current_pos += sizeof(dst_addr);
};
RegisterCode reg_code = 0;
readRegisterCode(reg_code);
u64 cond_reg_value = 0;
VM_registerRead(vm, &cond_reg_value, reg_code);
if(cond_reg_value == 0){
vm->current_pos = dst_addr;
}
return sizeof(dst_addr) + sizeof(cond_register_i);
return sizeof(dst_addr) + sizeof(reg_code);
}

17
src/instructions/impl/MOVC.c
View File

@@ -2,16 +2,11 @@
/// MOVC [dst_register] [value_size] [value]
i32 MOVC_impl(VM* vm){
u8 dst_register_i = 0;
readRegisterVar(dst_register_i);
/*u8 value_size = 0;
readValueSizeVar(value_size);*/
u8 value_size = 4;\
RegisterCode dst_reg_code = 0;
readRegisterCode(dst_reg_code);
u64 const_value = 0;
readVar(const_value);
vm->registers.array[dst_register_i].u64v = 0;
if(!VM_dataRead(vm, &vm->registers.array[dst_register_i].u64v, vm->current_pos, value_size))
return -1;
vm->current_pos += value_size;
return sizeof(dst_register_i) + sizeof(value_size) + value_size;
VM_registerWrite(vm, &const_value, dst_reg_code);
return sizeof(dst_reg_code) + sizeof(const_value);
}

17
src/instructions/impl/MOVR.c
View File

@@ -2,15 +2,16 @@
/// MOVR [dst_register] [src_register]
i32 MOVR_impl(VM* vm){
u8 dst_register_i = 0;
readRegisterVar(dst_register_i);
u8 src_register_i = 0;
readRegisterVar(src_register_i);
if(dst_register_i == src_register_i){
VM_setError(vm, "dst_register_i == src_register_i (%x) ", src_register_i);
RegisterCode dst_reg_code = 0, src_reg_code = 0;
readRegisterCode(dst_reg_code);
readRegisterCode(src_reg_code);
if(dst_reg_code == src_reg_code){
VM_setError(vm, "dst_reg_code == src_reg_code (%x) ", src_reg_code);
return -1;
}
vm->registers.array[dst_register_i].u64v = vm->registers.array[src_register_i].u64v;
return sizeof(dst_register_i) + sizeof(src_register_i);
u64 src_reg_value = 0;
VM_registerRead(vm, &src_reg_value, src_reg_code);
VM_registerWrite(vm, &src_reg_value, dst_reg_code);
return sizeof(dst_reg_code) + sizeof(src_reg_code);
}

34
src/instructions/impl/SYS.c
View File

@@ -1,6 +1,6 @@
#include "impl_macros.h"
FILE* NULLABLE(fileFromN)(VM* vm, u32 file_n){
FILE* NULLABLE(fileFromN)(VM* vm, u8 file_n){
FILE* f = NULL;
switch(file_n){
case 0: f = stdin; break;
@@ -15,13 +15,13 @@ FILE* NULLABLE(fileFromN)(VM* vm, u32 file_n){
}
// sys_read
// bx - file n
// cx - buffer ptr
// dx - buffer size
// ah - file n
// rbx - buffer ptr
// ecx - buffer size
i32 SYS_read(VM* vm){
const u32 file_n = vm->registers.b.u32v0;
u8* const buf = vm->data + vm->registers.c.u32v0;
const u32 size = vm->registers.d.u32v0;
const u8 file_n = vm->registers.a.h;
u8* const buf = vm->data + vm->registers.b.rx;
const u32 size = vm->registers.c.ex;
if(buf + size > vm->data + vm->data_size)
return 40;
@@ -31,13 +31,13 @@ i32 SYS_read(VM* vm){
}
// sys_write
// bx - file n
// cx - buffer ptr
// dx - buffer size
// ah - file n
// rbx - buffer ptr
// ecx - buffer size
i32 SYS_write(VM* vm){
const u32 file_n = vm->registers.b.u32v0;
u8* const buf = vm->data + vm->registers.c.u32v0;
const u32 size = vm->registers.d.u32v0;
const u8 file_n = vm->registers.a.h;
u8* const buf = vm->data + vm->registers.b.rx;
const u32 size = vm->registers.c.ex;
if(buf + size > vm->data + vm->data_size)
return 41;
@@ -47,10 +47,10 @@ i32 SYS_write(VM* vm){
}
/// SYS
/// before call: ax - func code
/// after call: ax - result code
/// before call: al - func code
/// after call: eax - result code
i32 SYS_impl(VM* vm){
u32 func_code = vm->registers.a.u32v0;
u8 func_code = vm->registers.a.l;
i32 result_code = 0;
switch(func_code){
case 0:
@@ -64,6 +64,6 @@ i32 SYS_impl(VM* vm){
return -1;
}
vm->registers.a.u64v = result_code;
vm->registers.a.ex = result_code;
return 0;
}

60
src/instructions/impl/impl_macros.h
View File

@@ -8,29 +8,55 @@
vm->current_pos += sizeof(VAR);\
}
#define validateRegisterIndex(VAR) {\
if(VAR> sizeof(vm->registers)){\
#define validateRegisterCode(VAR) \
if(VAR == RegisterCode_Unset || VAR > RegisterCode_dh){\
VM_setError(vm, "invalid register index (%x)", VAR);\
return -1;\
}\
}
}
#define readRegisterVar(VAR) {\
#define readRegisterCode(VAR) {\
readVar(VAR);\
VAR -= 1;\
validateRegisterIndex(VAR);\
validateRegisterCode(VAR);\
}
/*
#define validateValueSize(VAR) {\
if(VAR < 1 || VAR > 8){\
VM_setError(vm, "invalid value_size (%x)", VAR);\
return -1;\
}\
#define OPERATOR_IMPL_1(NAME, OPERATOR)\
i32 NAME##_impl (VM* vm) {\
RegisterCode dst_reg_code = 0;\
readRegisterCode(dst_reg_code);\
u64 dst_reg_value = 0;\
VM_registerRead(vm, &dst_reg_value, dst_reg_code);\
\
dst_reg_value = OPERATOR dst_reg_value;\
VM_registerWrite(vm, &dst_reg_value, dst_reg_code);\
return sizeof(dst_reg_code);\
}
#define readValueSizeVar(VAR) {\
readVar(VAR);\
validateValueSize(VAR);\
#define OPERATOR_IMPL_2(NAME, OPERATOR)\
i32 NAME##_impl (VM* vm) {\
RegisterCode dst_reg_code = 0, src_reg_code = 0;\
readRegisterCode(dst_reg_code);\
readRegisterCode(src_reg_code);\
u64 dst_reg_value = 0, src_reg_value = 0;\
VM_registerRead(vm, &dst_reg_value, dst_reg_code);\
VM_registerRead(vm, &src_reg_value, src_reg_code);\
\
dst_reg_value = dst_reg_value OPERATOR src_reg_value;\
VM_registerWrite(vm, &dst_reg_value, dst_reg_code);\
return sizeof(dst_reg_code) + sizeof(src_reg_code);\
}
#define OPERATOR_IMPL_3(NAME, OPERATOR)\
i32 NAME##_impl (VM* vm) {\
RegisterCode dst_reg_code = 0, src0_reg_code = 0, src1_reg_code = 0;\
readRegisterCode(dst_reg_code);\
readRegisterCode(src0_reg_code);\
readRegisterCode(src1_reg_code);\
u64 dst_reg_value = 0, src0_reg_value = 0, src1_reg_value = 0;\
VM_registerRead(vm, &dst_reg_value, dst_reg_code);\
VM_registerRead(vm, &src0_reg_value, src0_reg_code);\
VM_registerRead(vm, &src1_reg_value, src1_reg_code);\
\
dst_reg_value = src0_reg_value OPERATOR src1_reg_value;\
VM_registerWrite(vm, &dst_reg_value, dst_reg_code);\
return sizeof(dst_reg_code) + sizeof(src0_reg_code) + sizeof(src1_reg_code);\
}
*/

115
src/instructions/impl/logical_operators.c
View File

@@ -1,93 +1,36 @@
#include "impl_macros.h"
#define logicalOperator1Impl(NAME, OPERATOR)\
i32 NAME##_impl (VM* vm) {\
u8 src_register_i = 0;\
readRegisterVar(src_register_i);\
/*u8 value_size = 0;\
readValueSizeVar(value_size);*/\
u8 value_size = 4;\
\
switch(value_size){\
case 1: \
vm->registers.array[src_register_i].u8v0 = OPERATOR vm->registers.array[src_register_i].u8v0;\
break;\
case 2: \
vm->registers.array[src_register_i].u16v0 = OPERATOR vm->registers.array[src_register_i].u16v0;\
break;\
case 4: \
vm->registers.array[src_register_i].u32v0 = OPERATOR vm->registers.array[src_register_i].u32v0;\
break;\
case 8: \
vm->registers.array[src_register_i].u64v = OPERATOR vm->registers.array[src_register_i].u64v;\
break;\
}\
return sizeof(src_register_i) /*+ sizeof(value_size)*/;\
}
/// NOT [dst_register]
OPERATOR_IMPL_1(NOT, !)
#define logicalOperator2Impl(NAME, OPERATOR)\
i32 NAME##_impl (VM* vm) {\
u8 dst_register_i = 0, src_register_i = 0;\
readRegisterVar(dst_register_i);\
readRegisterVar(src_register_i);\
/*u8 value_size = 0;\
readValueSizeVar(value_size);*/\
u8 value_size = 4;\
\
switch(value_size){\
case 1: \
vm->registers.array[dst_register_i].u8v0 OPERATOR##= vm->registers.array[src_register_i].u8v0;\
break;\
case 2: \
vm->registers.array[dst_register_i].u16v0 OPERATOR##= vm->registers.array[src_register_i].u16v0;\
break;\
case 4: \
vm->registers.array[dst_register_i].u32v0 OPERATOR##= vm->registers.array[src_register_i].u32v0;\
break;\
case 8: \
vm->registers.array[dst_register_i].u64v OPERATOR##= vm->registers.array[src_register_i].u64v;\
break;\
}\
return sizeof(dst_register_i) + sizeof(src_register_i) /*+ sizeof(value_size)*/;\
}
/// INV [dst_register]
OPERATOR_IMPL_1(INV, ~)
#define logicalOperator3Impl(NAME, OPERATOR)\
i32 NAME##_impl (VM* vm) {\
u8 dst_register_i = 0, src0_register_i = 0, src1_register_i = 0;\
readRegisterVar(dst_register_i);\
readRegisterVar(src0_register_i);\
readRegisterVar(src1_register_i);\
/*u8 value_size = 0;\
readValueSizeVar(value_size);*/\
u8 value_size = 4;\
\
switch(value_size){\
case 1: \
vm->registers.array[dst_register_i].u8v0 = vm->registers.array[src0_register_i].u8v0 OPERATOR vm->registers.array[src1_register_i].u8v0;\
break;\
case 2: \
vm->registers.array[dst_register_i].u16v0 = vm->registers.array[src0_register_i].u16v0 OPERATOR vm->registers.array[src1_register_i].u16v0;\
break;\
case 4: \
vm->registers.array[dst_register_i].u32v0 = vm->registers.array[src0_register_i].u32v0 OPERATOR vm->registers.array[src1_register_i].u32v0;\
break;\
case 8: \
vm->registers.array[dst_register_i].u64v = vm->registers.array[src0_register_i].u64v OPERATOR vm->registers.array[src1_register_i].u64v;\
break;\
}\
return sizeof(dst_register_i) + sizeof(src0_register_i) + sizeof(src1_register_i) /*+ sizeof(value_size)*/;\
}
logicalOperator3Impl(EQ, ==)
logicalOperator3Impl(NE, !=)
logicalOperator3Impl(LT, <)
logicalOperator3Impl(LE, <=)
logicalOperator3Impl(GT, >)
logicalOperator3Impl(GE, >=)
/// OR [dst_register] [src_register]
OPERATOR_IMPL_2(OR, |)
logicalOperator1Impl(NOT, !)
logicalOperator1Impl(INV, ~)
/// XOR [dst_register] [src_register]
OPERATOR_IMPL_2(XOR, ^)
logicalOperator2Impl(OR, |)
logicalOperator2Impl(XOR, ^)
logicalOperator2Impl(AND, &)
/// AND [dst_register] [src_register]
OPERATOR_IMPL_2(AND, &)
/// EQ [dst_register] [src0_register] [src1_register]
OPERATOR_IMPL_3(EQ, ==)
/// NE [dst_register] [src0_register] [src1_register]
OPERATOR_IMPL_3(NE, !=)
/// LT [dst_register] [src0_register] [src1_register]
OPERATOR_IMPL_3(LT, <)
/// LE [dst_register] [src0_register] [src1_register]
OPERATOR_IMPL_3(LE, <=)
/// GT [dst_register] [src0_register] [src1_register]
OPERATOR_IMPL_3(GT, >)
/// GE [dst_register] [src0_register] [src1_register]
OPERATOR_IMPL_3(GE, >=)

36
src/instructions/impl/math_operators.c
View File

@@ -1,42 +1,16 @@
#include "impl_macros.h"
#define mathOperator2Impl(NAME, OPERATOR)\
i32 NAME##_impl (VM* vm) {\
u8 dst_register_i = 0, src_register_i = 0;\
readRegisterVar(dst_register_i);\
readRegisterVar(src_register_i);\
/*u8 value_size = 0;\
readValueSizeVar(value_size);*/\
u8 value_size = 4;\
\
switch(value_size){\
case 1: \
vm->registers.array[dst_register_i].u8v0 OPERATOR##= vm->registers.array[src_register_i].u8v0;\
break;\
case 2: \
vm->registers.array[dst_register_i].u16v0 OPERATOR##= vm->registers.array[src_register_i].u16v0;\
break;\
case 4: \
vm->registers.array[dst_register_i].u32v0 OPERATOR##= vm->registers.array[src_register_i].u32v0;\
break;\
case 8: \
vm->registers.array[dst_register_i].u64v OPERATOR##= vm->registers.array[src_register_i].u64v;\
break;\
}\
return sizeof(dst_register_i) + sizeof(src_register_i) /*+ sizeof(value_size)*/;\
}
/// ADD [dst_register] [src_register]
mathOperator2Impl(ADD, +)
OPERATOR_IMPL_2(ADD, +)
/// SUB [dst_register] [src_register]
mathOperator2Impl(SUB, -)
OPERATOR_IMPL_2(SUB, -)
/// MUL [dst_register] [src_register]
mathOperator2Impl(MUL, *)
OPERATOR_IMPL_2(MUL, *)
/// DIV [dst_register] [src_register]
mathOperator2Impl(DIV, /)
OPERATOR_IMPL_2(DIV, /)
/// MOD [dst_register] [src_register]
mathOperator2Impl(MOD, %)
OPERATOR_IMPL_2(MOD, %)